1. Field of the Invention
The present invention is in the field of semiconductor structures. The present invention is further in the field of semiconductor structures of transistor devices and manufacture processes. The present invention further relates to the field of integrated devices and circuits. The implementation is not limited to a specific technology, and applies to either the invention as an individual component or to inclusion of the present invention within larger systems which may be combined into larger integrated circuits.
2. Brief Description of Related Art
Silicon and III-V materials IC technologies are traditionally distinguished by their unique and often exclusive characteristics. While Si technology is more mature and uses more established processes that enable a much higher level of integration, its device speed is relatively limited. III-V based technologies, such as Gallium Arsenide (GaAs) and Gallium Nitride (GaN), on the other hand, offer much faster device speed as well as light-emitting capability. However, III-V compounds semiconductors suffer from extreme sensitivity to processing and a lack of established processes, limiting the circuit integration to much lower levels than for Si IC's.
III-V compounds based devices such as Light Emitting Diodes (LED) and High Electron Mobility Transistors (HEMTs) are usually grown on sapphire (Al203), silicon carbide (SiC) or Germanium (Ge) substrates depending on the physical properties of the III-V crystal. Nevertheless, the growth of device-quality III-V based hetero-structures on silicon substrates is of huge interest in terms of cost, availability, processing and integration. Hybrid circuits are promising candidates for use in power applications as well as for optical applications. Examples hereof include the manufacture of light emitting diodes, power amplifiers, power converters, etc. In particular, high frequency power converter and RF applications can greatly benefit from the use of these new type of integrated circuits.
Hexagonal GaN, for instance, has been already successfully deposited on Si (111) substrates either by metal-organic chemical vapor deposition (MOCVD) or by molecular beam epitaxy (MBE) methods, in spite of the difficulties related to the very high reactivity of the silicon surface with nitrogen, the large lattice mismatch (−16.2%) and the large difference in thermal expansion coefficient (113%). However, from the point of view of integrating GaN devices with silicon technology, the Si (100) substrate is preferred because it is the most widely used in silicon mainstream technology. Generally however, a mixture of cubic and hexagonal GaN tends to grow on Si (100) substrate, with the cubic poly-type being the dominant phase, which significantly decreases the device performance.
The main difficulty in growing GaN on Si is the stress that develops during growth. Cracks occur even for epi-layer thickness of about 1 um. Therefore, to obtain GaN based devices, it is important to minimize the strain. For optoelectronic devices, a thick layer with good electro-optical and structural properties is required and these are also the basic criteria for transistors. Also, to achieve high carrier mobility the interface should be defect free, abrupt and smooth. This is achievable only for epitaxial-layers well above 1 um in thickness.
Patterning substrates by masking or etching the substrates or buffer layers are low cost but highly effective ways to reduce the stress or cracks. Dislocations or cracks will be guided in the masked or etched layer and will leave the epitaxial layer with low density of dislocations or cracks. In this technique, a Silicon Nitride (Si3N4) or a Silicon Dioxide (SiO2) layer is deposited over the Silicon substrate in a patterned manner or deep trenches are made on the masked materials. The exposed surfaces are usually misoriented from the 100 substrate in order to improve the crystal quality and therefore the performance of the III-V based devices.
Some previous work suggests that, for example, the use of Si (100) substrates tilted by more than 4° towards [011] is effective to prevent the formation of two domains during the growth of AlN and GaN. By enabling the growth of a pure hexagonal GaN layer similar results were obtained for the growth of GaAs on Si wafers misoriented from the singular plane (001) by 4-6 arc degrees. Using a misorientation of about 54 degrees, the compound material can be also grown directly on the (111) Si direction, significantly improving the crystal quality.
An example of this technique is reported in Hopper at al. (US 2010/0140663) where the manufacturing of a discrete AlGaN/GaN HEMT formed on a <100> orientation silicon wafer is described. In this patent application, the authors use a trench with walls slanted at 54 degrees etched into the silicon to provide a <111> orientation substrate surface for forming the AlGaN channel transistor.
The growth of purely hexagonal GaN on Si (100) Substrates can be achieved also by employing one sputtered aluminum nitride (AlN) buffer layer followed by another high-temperature MOCVD grown AlN buffer layer. An AlGaN buffer layer can be also added over the AlN seed layer in order to improve the quality of the GaN crystal. The AlGaN layer increases the series resistance and generates compressive stresses in the GaN layer, which helps reduce cracks in the layer and provides good electrical insulation from the substrates. So the efficiency of high frequency transistors and vertically contacted LEDs will increase.
Another potential advantageous buffer material is the Zinc Oxide (ZnO), which is isomorphic with wurtzite GaN, with only 1.8% lattice mismatch with respect to GaN. In fact, they have already been used as buffer layers for each other. Chemical Vapor Deposition (CVD), and Molecular Beam Epitaxy (MBE), have been utilized to grow ZnO-buffered GaN films on various substrates. Particularly high-quality GaN films on ZnO have been obtained through an ion-beam-assisted filtered cathodic vacuum arc (I-FCVA) technique. This technique offers several advantages as it is versatile, more flexible, and more cost effective than the most widely used MOCVD and MBE techniques. The FCVA technique employs a curved magnetic field to guide the plasma generated from the cathodic vacuum arc to deposit on substrates, using a mechanical filtering technique to remove unwanted macroparticles and neutral atoms. Only ions within a defined energy range reach the substrates, thus producing films with good controllability and reproducibility. On the other hand, the ion beam source can generate energetic nitrogen ions from nitrogen gas, which effectively enhances the formation of the GaN.
Other very good techniques to grow a III-V layer on Silicon substrate comprise Pulsed laser deposition (PLD) and Pulsed Plasma Deposition (PPD) techniques. PLD is a thin film deposition (specifically a physical vapor deposition, PVD) technique where a high power pulsed laser beam is focused inside a vacuum chamber to strike a target of the material that is to be deposited. This material is vaporized from the target (in a plasma plume) which deposits it as a thin film on a substrate (such as a silicon wafer facing the target). This process can occur in ultra high vacuum or in the presence of a background gas.
While the basic setup is simple relative to many other deposition techniques, the physical phenomena of laser-target interaction and film growth are quite complex. When the laser pulse is absorbed by the target, energy is first converted to electronic excitation and then into thermal, chemical and mechanical energy resulting in evaporation, ablation, plasma formation and even exfoliation. The ejected species expand into the surrounding vacuum in the form of a plume containing many energetic species including atoms, molecules, electrons, ions, clusters, particulates and molten globules, before depositing on the typically hot substrate.
PPD is a low temperature processes physical vapor deposition technique proved to deposit thin films of numerous materials such as oxides, complex oxides, nitrides, carbides, carbon based films, semiconductors, etc. PPD produces a pulsed high density electron beam (500 MW/cm2) which, by interacting with the target, causes material ablation independently of the energy gap (i.e. the optical absorption) of the target itself. The chemical composition of the target is transferred to the substrate by a supersonic highly energetic plasma giving rise to thin films of materials otherwise impossible to grow with conventional PVD and CVD techniques.
In general, also the co-integration of other III-V materials, such as GaAs, with CMOS IC present the same issued discussed above in particular for GaN technologies. There have been many studies of alternative growth approaches (MBE, MOCVD, etc.), as well as different procedures used within each general deposition approach, to minimize defect densities and cross-contaminations between the two technologies. Despite these many studies, the high risk of cross-contamination and the defect density limit the manufacture of hybrid integrated circuits. There are indeed many issues associated with the thermal budget of the combined processes and with the quality of the III-V epitaxial layers, which has not been solved yet.
An example of co-integration of III-V materials with a standard CMOS technology is reported in Augustine et al. in (US 2006/0284247), where the authors disclose the integration of AlGaN/GaN amplifiers with silicon CMOS circuits. A planarization layer of amorphous or polycrystalline silicon and a thin layer of single crystalline silicon were formed on a SiC substrate. Thereafter, a GaN heterostructure comprising AlGaN and GaN layers was grown epitaxially. A protection layer of silicon nitride or silicon oxide was deposited on the GaN heterostructure. Following this, a silicon layer is bonded to the protection layer particularly in the form of an SOI substrate with its top layer bonded to the passivation layer. The SOI substrate is thereafter thinned so as to remove its handling wafer and its buried oxide. The resulting silicon device layer typically has a thickness of 50 to 200 nm. A first device area for the definition of GaN devices was defined, and the silicon is etched away in those areas. Following this, CMOS devices are fabricated on the silicon layer in a second device area, and GaN devices are fabricated on the GaN hetero structure.
Even if this method enables the co-integration of two different technologies, it has the disadvantage that the bonding process is still delicate, and may not result in a strong bond. Furthermore, it preferably applies grooves into one or more of the layers at the bonding interface so as to remove residual gases from the interface. These grooves are particularly needed at the center of the wafer, where otherwise the bond would not be good enough. The grooves are typically at a pitch between 1 and 2 um. This however implies that the pitches will be present within the final chip, and thus the amount of available surface area decreases.
An interesting solution to this problem has been proposed by Cheng et al. (US 2011/0108850), where a substrate for hybrid integrated circuits comprising both GaN and Si devices, is disclosed. This substrate comprises a GaN-heterostructure in a first device area for definition of GaN-based devices, which hetero-structure is covered partially with a protection layer; and a semiconductor substrate layer in a second device area for definition of CMOS devices. The GaN heterostructure and the semiconductor substrate layer are provided in one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed.
Even if this solution has the advantage that the integrated semiconductor substrate structure may be provided with a substantially planarized surface, it still does not solve the problem related to the different thermal budgets needed for the III-V process and the CMOS devices. In this patent application, the authors indeed disclose the fabrication of a semiconductor substrate containing a GaN heterostructure which should be utilized to process the CMOS technology. The high temperature annealing steps required from the CMOS process could lead to the diffusion of Silicon atoms in the GaN layer, decreasing the GaN-based device performances.
The prior art attempts described above have therefore several drawbacks and are not industrially viable. It is indeed desirable to provide an improved hybrid integrated circuit which is not sensitive to diffusion of silicon and/or oxide particles into the GaN layers. It is also desirable to provide an improved method for the manufacturing of this integrated semiconductor structure in which III-V devices can be defined in at least a first device area and on which CMOS circuits can be defined in a separate area, preventing the cross contaminations of the two or more processes due to the different thermal budget of the technologies used. It is also desirable to provide an improved method of manufacturing an integrated circuit with both III-V and CMOS devices and to provide improved devices.
It is therefore a purpose of the present invention to describe a novel hybrid integrated circuit that offers the advantage of combining different semiconductor technologies with high density, reducing semiconductor area and cost combined with improved performances in terms of on resistance and frequency response.
This invention enables the consolidation on the same integrated circuit of a hybrid switching power converter that takes advantage of the established circuit topologies of CMOS circuitries and of the higher mobility and voltage withstanding of III-V HEMT devices.